These circuits are formed by NMOS and PMOS transistors.
Realization of a NAND gate:
1 <=> Vcc (5V for example)
0 <=> GND (0V)
We can very well draw up this table to analyze the operation of the circuit:
|A B||Vgs_Q1 Q1||Vgs_Q2 Q2||Vgs_Q4 Q4||Vg_Q3 Vs_Q3||Vgs_Q3 Q3||V(Y) Y|
|0 0||-5V conduct||-5V conduct||0 blocked||0 ?||? ?||Vcc 1|
|0 1||-5V conduct||0 blocked||5V conduct||0 0||0 blocked||Vcc 1|
|1 0||0 blocked||-5V conduit||0 blocked||5 ?||? ?||Vcc 1|
|1 1||0 blocked||0 blocked||5V conduct||5 0||5V blocked||0 0|
We find the operation of a NAND!
Q3 being upstream of Q4, when the latter is blocked (equivalent to an open switch) then the source of Q3 is found in a floating state: we cannot determine the value of its potential. Hence the “?” In the table. But this has no influence on the determination of the state of output Y.