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C-MOS logic integrated circuits

These circuits are formed by NMOS and PMOS transistors.

Realization of a NAND gate:

C-MOS logic integrated circuits

Quick scan:

    1 <=> Vcc (5V for example)
    0 <=> GND (0V)

We can very well draw up this table to analyze the operation of the circuit:

A        BVgs_Q1          Q1Vgs_Q2          Q2Vgs_Q4          Q4Vg_Q3          Vs_Q3Vgs_Q3          Q3V(Y)          Y
0          0-5V          conduct-5V          conduct0             blocked0                    ??                 ?Vcc            1
0          1-5V          conduct0             blocked5V          conduct0                    0   0           blockedVcc            1
1          0 0             blocked-5V          conduit0             blocked5                    ??                 ?Vcc            1
1          1 0             blocked0             blocked5V          conduct5                    0  5V          blocked 0               0

We find the operation of a NAND!

Note :

Q3 being upstream of Q4, when the latter is blocked (equivalent to an open switch) then the source of Q3 is found in a floating state: we cannot determine the value of its potential. Hence the “?” In the table. But this has no influence on the determination of the state of output Y.

Circuits intégrés
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