1- Presentation :
The CQM1 is a compact OMRON Industrial Programmable Logic Controller (PLC), programmable with SYSWIN software, consisting of a power supply, a central unit (CPU) and I / O boards. All of these cards connect on the side to form a single PLC that typically mounts on a DIN rail.
All CQM1 CPUs, except CQM1-CPU11-E, are equipped with an RS-232C port which can be connected directly to a computer, another CQM1, or other serial devices.
ABS interface function: The CQM1-CPU44-E CPU is equipped with two ABS interfaces (absolute encoder interfaces) which can directly receive inputs from absolute rotary encoders (max. 1 kHz).
2- programmation :
2 .1- Compatible programming consoles
Two programming consoles can be used with the CQM1: the CQM1-PRO01-E and the C200H-PRO27-E. The basic functions of these programming consoles are identical.
2.2- The SYSWIN software:
The “SYSWIN” software allows programming of “OMRON-CQM1” PLCs used in many automated systems. Addressing (coding of input, output and intermediate variables) and the definition of some logic instructions are presented below.
3– Structure of the memory area
4- Basic procedure
There are several basic steps involved in writing a program :
- List all I / O devices and I / O points and prepare a table showing the I / O bit assigned to each I / O device.
- Determine which words are available for the work bits and prepare an allocation table for these according to their use.
- Draw the ladder diagram.
- Enter the program in the central unit. Using the programming console involves converting the program into mnemonic form.
- Check the program for syntax errors and correct them.
- Run the program to check for runtime errors and correct them.
- After installation of the complete control system and when it is ready for use, run the program and make the necessary adjustments.
5- Instruction terminology
There are two types of ladder diagram instructions:
- Instructions that correspond to conditions, used as instructions only when converting to mnemonic.
- The instructions used on the right side of the diagram, executed according to the conditions found on the instruction lines.
Most instructions have at least one associated operand. Operands provide information regarding the execution of an instruction. They are sometimes entered as real numeric values but generally correspond to zone channel addresses or to bits containing data to be used.
6- The basics of the ladder diagram
A ladder diagram consists of a down line on the left side with lines branching out to the right. The line on the left is called the bus bar. The branch lines are called the instruction lines. Along the instruction lines are the conditions leading to further instructions on the right side. The logical combinations of these conditions determine when and how the instructions on the right are executed. A ladder diagram is shown below:
6.1- Fundamental terminology
Each condition in a ladder diagram is ON or OFF depending on the state of the operand bit assigned to it. A normally open condition is ON if the operand bit is ON; to OFF if the operand bit is OFF. A normally closed condition is ON if the operand bit is OFF; to OFF if the operand bit is ON.
6.2- Mnemonic code
To program a CQM1 PLC using the programming console, it is necessary to convert the ladder diagram into a mnemonic. The mnemonic code provides exactly the same information as the ladder diagram but in a form that can be entered directly into the PLC. You can program directly in mnemonic code but this is not recommended in the case of complex programs.
Whatever the programming device, the program is stored in memory in mnemonic form, hence the importance of this code.
The program is presented in the program memory in the form of addresses. Each address contains an instruction and all operand data and operands necessary for that instruction. Some instructions do not require operands and others up to 3 operands. Program memory addresses start at 00000 and run until capacity is exhausted.
Here is an example of mnemonic code; the instructions used will be described later:
6.2.1- LOAD and LOAD NOT
The first condition of a logic block in a ladder diagram corresponds to a LOAD or LOAD NOT instruction. Each of these instructions requires a line of mnemonic code.
6.2.2- AND and AND NOT
When several conditions are in series on the same row, the first corresponds to a LOAD or LOAD NOT statement and the others to AND or AND NOT statements. The following example shows three conditions corresponding from left to right to LOAD, AND NOT, and AND statements. Each of these instructions requires a line of mnemonic code.
6.2.3- OR and OR NOT
When several conditions are present on separate but parallel instruction lines and meet, the first corresponds to a LOAD or LOAD NOT instruction; the rest of the conditions correspond to an OR or OR NOT instruction. The following example shows three conditions corresponding from top to bottom to LOAD NOT, OR NOT, and OR statements.
6.2.4- Combination of AND and OR instructions
When AND and OR instructions are combined in more complex schemes, they can sometimes be viewed individually, with each instruction performing a logical operation on the condition and the state of the operand bit. In more complicated diagrams, however, it is necessary to consider the logic blocks before being able to determine the execution condition of the final instruction.
6.2.5- OUTPUT and OUTPUT NOT
The easiest way to output the results of a combination of conditions is to do so directly with OUTPUT and OUTPUT NOT. These instructions are used to check the state of the designated operand bit according to the execution condition. With the OUTPUT instruction, the operand bit turns ON (or OFF) respectively as long as the condition is ON (or OFF).
6.2.6- The END instruction
The last instruction in a simple program is END. When the CPU scans the program, it executes all instructions up to the first END instruction and returns to the start of the program to restart execution. Although an END instruction can be placed anywhere in the program, which is sometimes done during debugging, no instruction beyond END will be executed. The number following the END instruction in mnemonic code is its function code, used when entering most instructions into the API. The END instruction does not need any operands and no condition can be placed on the same line. If there is no END instruction in the program, the program is not executed.
6.2.7- Logic block instructions
Logic block instructions do not correspond to any specific condition on the ladder diagram but describe relationships between logic blocks. AND LOAD establishes a logical AND between the execution conditions produced by two logical blocks; OR LOAD establishes a logical OR between the conditions produced by two logical blocks.
Although apparently simple, the diagram below requires an AND LOAD statement. The two logic blocks appear in dotted lines. This example shows
that an ON execution condition is produced when one of the conditions in the left block is ON (IR 00000 or IR 00001 is ON) and when one of the conditions in the right block is ON ( IR 00002 is ON or IR 00003 is OFF).
The following diagram requires an OR LOAD instruction between the top logic block and the bottom logic block. An ON execution condition is produced for the right instruction when IR 00000 is ON and IR 00001 is OFF or when IR 00002 and IR 00003 are ON. The operation and mnemonic code of OR LOAD are exactly the same as those of AND LOAD, except that the current execution condition is linked by OR with the last unused condition.
Combination of AND LOAD and OR LOAD
Block b below cannot be coded without being separated into two blocks combined by OR LOAD. In this example, the three blocks were coded first and OR LOAD was then used to combine the last two blocks, then AND LOAD to combine the execution condition produced by OR LOAD with the execution condition of block a.
When determining the logic instructions necessary for coding a diagram, it is sometimes necessary to divide the latter into large blocks and then in turn divide these blocks to arrive at logic blocks which can be coded without forming instructions into logic blocks. These blocks are then coded by combining the small blocks first and then the larger blocks. AND LOAD or OR LOAD is used for the combination of blocks: they always combine the last two execution conditions, whether they result from a single condition, from logical blocks or from previous logical block instructions.
In complicated diagrams, the blocks are coded starting from the top left and then going down. When we have the choice, we therefore code OR LOAD before AND LOAD.
The following diagram should be split into two blocks and each block into two other blocks before coding. As can be seen, blocks a and b require an AND LOAD instruction. Before AND LOAD, however, OR LOAD must be used to combine the top and bottom blocks of both sides, i.e. to combine a1 and a2 as well as b1 and b2.
6.2.8- Coding of multiple right-hand instructions
If several right-hand instructions are executed with the same execution condition, they are coded successively after the last one.
condition of the row. In the following example, the last instruction line contains an additional instruction corresponding to an AND with IR 00004.
6.2.9- Secondary lines
When an instruction line splits into two or more other branch lines, it is sometimes necessary to use branches or TR bits to maintain the run condition that existed at the branch.
In this example, TR 0 and TR 1 are used to store the execution conditions at the branch point. After the execution of instruction 1, the condition stored in TR 1 is loaded to perform an AND with the state of IR 00003. The execution condition stored in TR 0 is loaded twice, the first to perform an AND. with the state of IR 00004 and the second with the inverted state of IR 00005.
6.3- Checking bit status
You can use 7 basic instructions to individually control the state of the bits: OUTPUT, OUTPUT NOT, SET, RESET, DIFFERENTIATE UP, DIFFERENTIATE
DOWN and KEEP. All of these instructions appear at the end of an instruction line and have a bit address as an operand.
6.3.1- SET and RESET
SET and RESET instructions are very similar to OUTPUT and OUTPUT NOT instructions, except that they change the state of their operand bits for execution conditions to ON. Neither of these two instructions affects the state of its operand bit when the execution condition is OFF.
- SET sets its operand bit to ON when the execution condition turns ON, but unlike the OUTPUT instruction, SET does not set the operand bit to OFF when the execution condition turns OFF.
- RESET sets the operand bit to OFF when the execution condition is OFF, but unlike OUTPUT NOT, RESET does not turn the operand bit ON when the execution condition turns OFF.
6.3.2- DIFFERENTIATE UP and DIFFERENTIATE DOWN
The DIFFERENTIATE UP (rising edge) and DIFFERENTIATE DOWN (falling edge) instructions are used to set the operand bit ON for one scan revolution at a time.
- DIFFERENTIATE UP sets the operand bit to ON for one scan round after its execution condition has changed from OFF to ON;
- DIFFERENTIATE DOWN sets the operand bit to ON for one scan round after its execution condition has changed from ON to OFF.
These two instructions only require one instruction line in mnemonic code.
KEEP is used to maintain the state of the operand bit resulting from two execution conditions. To do this, KEEP is connected to two instruction lines. When the execution condition of the end of the first line is ON (lock), the operand bit of KEEP is set to ON (unlock).
When the execution condition of the end of the second line is ON, the operand bit of KEEP is set to OFF (latching). The KEEP operand bit maintains its ON or OFF state even if it is located in a branch. The unlock bit takes priority over the lock bit.
6.4- Timing / counting instructions
TIM and TIMH (15) are decrementing on-delay timing instructions requiring a TC number and a selected value (SV).
STIM (––) is used to control the tempos. cyclic which are used to activate interrupt subroutines.
CNT is a decrementing counter instruction and CNTR is a reversible counter instruction. Both require a TC number and SV; they are connected to multiple instruction lines and serve as an input and reset signal. CTBL (––), INT (––) and PRV (––) are used to manage the high speed counter. INT (––) is also used to stop the pulse output.
Any TC number can only be defined twice, that is, once it has been used as an operand field in a tempo instruction. or counter,
it cannot be reused. Once defined, TC numbers can be used as many times as desired as operands in other instructions.
that tempo. or counter.
TC numbers range from 000 to 511. No prefix is needed when using a TC number as operand data in a tempo instruction. or counter. Once defined as a timer, a TC number can be prefixed with TIM to be used as an operand in certain instructions. The TIM prefix is used regardless of the timing instruction used to set the timing. Once defined as a counter, a TC number can be prefixed with CNT to be used as an operand in certain instructions. CNT can also be used regardless of the counter instruction used to set the counter.
6.4.1- TIMER – TIM
SV is between 000.0 and 999.9. The decimal point is not entered. Each TC number can be used as operand data in a single TIMER or COUNTER instruction. A timer activates when its execution condition turns ON and is reset (to SV) when the condition turns OFF. When activated, TIM measures in 0.1 second units from the SV.
6.4.2- COUNTER – CNT
CNT is used to count down from the SV when the count pulse condition, CP, changes from OFF to ON, that is, the current value (PV) is decremented by one each time. time that CNT is executed with an ON condition for the CP and the condition of the last execution was OFF. If the execution condition has not changed or has changed from ON to OFF, the PV of CNT remains unchanged. The end flag of a counter turns ON when the PV reaches zero and remains there until the counter is reset.
CNT is reset using a reset input, R. When R changes from OFF to ON, the PV is reset to the value of the SV. The PV is not decremented when R is ON. The downcounting from SV starts again when R turns OFF. The CNT CP is not reset in the connections or in the event of a power failure.
Here is an illustration of the above in the form of a diagram and corresponding mnemonic codes:
7- Quick diagnosis of the PLC
The following diagrams can be used to resolve possible operational problems.