Accueil > Electronic > Sequential logic circuits
ElectronicIndustrial automationThe basics of automation

Sequential logic circuits

A logic system is said to be “sequential” when one or more outputs are linked to one or more inputs. The system is thus closed. Thus, at an instant t, an output depends on the state of the inputs, but also on its own state at the instant t-1.

1. RS flip-flop

1.1. Elementary RS flip-flop

Production :

Elementary RS flip-flop



Truth table:

RSQn+1
00Qn (memory)
011
100
11State forbidden!

Explanations:

Let’s start by analyzing the states where R and S are different:

  • if R = 0 and S = 1: S = 1 => A = 0 => Q = 1 whatever B. Or Q = C = 1, moreover like R = 0 => D = 1 => / Q = /(1.1) = 0.
  • if R = 1 and S = 0: R = 1 => D = 0 => / Q = 1 whatever C. Or / Q = B = 1, moreover like S = 0 => A = 1 => Q = 0.

Let us now analyze the states where R and S are identical:

  • if R = S = 0: we therefore have A = D = 1, so we cannot comment on the state of the NANDs. In fact at an instant “n + 1”, the state of the NANDs will depend on the state of Q and of / Q at the previous instant “n” (this is the principle of sequential logic!).
    So :
    – if Q = 1 (=> / Q = 0) then B = 0 => Q = 1 and C = 1 => / Q = 0.
    – if Q = 0 (=> / Q = 1) then C = 0 => / Q = 1 and B = 1 => Q = 0.
    We therefore notice that when R = S = 0, the state of the outputs is unchanged: if R = S = 0 at an instant “n + 1” then the Q and / Q outputs will keep the state they had at l ‘previous instant “n” => Qn + 1 = Qn (and / Qn + 1 = / Q obviously). We say that the RS flip-flop is in “memory” state.
  • if R = S = 1: we therefore have A = D = 0 => Q = / Q = 1. So when we want to go from the state R = S = 1 => Q = / Q = 1 to l ‘state R = S = 0 => Qn + 1 = Qn then the outputs should remain unchanged (= 1).
    But in practice it is necessary to consider the switching times of the logical operators. Indeed, even if they come from the same manufacturer, their switching times will always be slightly different. So when we go from the state R = S = 1 to R = S = 0, one of the inputs A or B will go to 1 before the other, which will make either Q or / Q go to 0 But we cannot know which of A or B will be at 1 before the other, so we cannot precisely determine the state of the output … We say that there is an indeterminacy on the output. We therefore prefer to prohibit the combination R = S = 1!

1.2. RS flip-flop synchronized


The operation is the same as that of an elementary RS flip-flop. Only the changes of state will be synchronized by a clock “clk” (clock = clock in English).

Realization :

Synchronized RS flip-flop

Note: / Preset and / Clear are priority commands. They are independent of the “clk” clock: when / Preset = 0, then Q = 1 (instantaneously) and when / Clear = 0, then Q = 0 (instantaneously).
Of course, to represent an RS flip-flop in an electrical diagram, we will not redraw the assembly with the 4 NAND flip-flops. There is a symbol:

Synchronized RS flip-flop symbol

Note: the “small circles” shown on the / Preset and / Clear controls mean that these controls are active at low level (0).
Operation:

To explain the operation of the synchronized RS flip-flop, one can draw chronograms: i.e. the state of the outputs as a function of the state of the inputs over time:

chronograms

2. D flip-flop

We will see that this toggle can be used in 2 ways: as a “delay” or “lock” toggle (also called “latch”).

realization :

There are 2 ways of making a D flip-flop. They are completely equivalent:

2. D flip-flop

    Symbole :

D flip-flop Symbol

Operation :
When the clock “clk” will go from 0 to 1, then the output Q will take the state of input D. We therefore have this truth table :

DQn+1
00
11

There are 2 types of operation: in “delay” or in “latch” :

2.1. Time limit

This operating mode makes it possible to delay the evolution of a signal: the output signal Q will take the state of the input signal D after a certain “delay” time given by the clock “clk”. Chronogram:

Time limit

2.2. Lock (or “Latch”)

In “lock” mode, output Q can either follow the evolution of input D, or remain in a memory state, depending on whether “clk” is at 1 or at 0. Chronogram :

Latch

Note: Finally, we see that the 2 operating modes simply differ by the clock signal. In “delay” the clock does not need a large cyclic ratio, while in “latch” it will be necessary to adapt this cyclic ratio according to the duration of the desired follower and memory states.

2.3. Edge triggered D flip-flop

The operation is the same as that of a “simple” D flip-flop, except that the information on the D input will only be taken into account on the rising edge (change from 0 to 1) of “clk” or on the falling edge (1 to 0). Unlike the previous case where the change was made on a logical state of “clk” (0 or 1: 1 in the example).

realization :

Let us take the example of a D flip-flop triggered by a rising edge :

Edge triggered D flip-flop

Symbol :

Edge triggered D flip-flop symbol

What changes from the symbol of a “simple” D flip-flop is the triangle on the “clk” clock. It indicates that input D is taken into account on the rising edge of the clock.

Note: for a D flip-flop triggered by a falling edge, the symbol is :

D flip-flop triggered by falling edge

We put a circle in front of the triangle of the clock “clk”: this means that we must consider the falling edge of the clock.

Operation :

The truth table remains the same, but the state of D is only taken into account on one edge of the clock (the rising edge in our example). So we can draw the following chronogram :

rising edge

3. JK and JK flip-flop with edge trigger

3.1. JK flip-flop

To quickly describe the operation of a JK flip-flop, we can say that it is an improved RS flip-flop. Indeed, the principle is the same (with J instead of S and K instead of R) but there is no longer an undetermined state! Indeed when J = K = 1, then the output Qn + 1 (Q at an instant n + 1) will take the inverse state of Qn (Q at the previous state n).

realization :

JK flip-flop

Symbol :

JK flip-flop symbol

Operation :

In the example studied, the changes of state of the output Q take place when the clock “clk” is at 0. The following truth table can be established:

JKQn+1
00Qn (memory)
010
101
11/Qn (“Toggle”)

 

  • if J = K = 0, then Qn + 1 = Qn. We say that the rocker operates in “memory” mode.
  • if J = 0 and K = 1, then Q = 0.
  • if J = 1 and K = 0, then Q = 1.
  • if J = K = 1, then Qn + 1 = / Qn. The state of Q is reversed, we say that the rocker operates in “Toggle” mode.

Note: as for the RS flip-flop, the / Pre (Preset) and / Clr (Clear) commands have priority: whatever the state of the inputs, if / Pre = 0 then Q = 1, and if / Clr = 0 then Q = 0.

3.2. Front triggered JK flip-flop

realization :

Front triggered JK flip-flop

Operation:

The operation is the same as before. Except that the changes of state of the output are made on an edge of “clk”: the rising edge for the example chosen.

Symbol :

JK flip-flop symbol with edge triggering

Notes:

     

  • the symbol is almost identical to that of the simple JK. We see that it is a JK rocker triggered by a rising edge thanks to the “small triangle” located on the “clk” entry.
  • in our example, the priority commands “Pre” and “Clr” are active in the high state (logic 1) unlike the previous case.
  • as I already mentioned, there are also JK rockers with triggering by falling edge. The symbol remains the same, except that you have to add the “small circle” on the entry of “clk”:
symbol JK flip-flop triggered by falling edge

It may interest you

Leave a Reply

Your email address will not be published. Required fields are marked *

Solve : *
27 × 6 =