TTL = Transistor Transistor Logic
The king element in this type of circuit is the bipolar transistor. The diodes present only provide a protection role for the circuits (against reverse voltages for example …).
Realization of a NAND gate:
Notes:
- the diodes are used to protect the circuits. For the analysis we can act as if the diodes D1 and D2 did not exist.
- element T1 is a transistor with 2 emitters. For the analysis we have the right to replace it with this:
Finally, with all these simplifications, we arrive at this equivalent circuit:
To note :
- In TTL logic, for a Vcc = 5V power supply, the logic levels are referenced by 2 threshold voltages: V0 (0.2V) and V1 (3.6V).
If the output voltage V (Y) is less than or equal to V0 then Y = 0, if V (Y) is greater than or equal to V1 then Y = 1:
– V (Y) = <0.2V we have Y = 0 – V (Y) => 3.6V we have Y = 1 - For the inputs, we will say that an input is at 0 if its voltage is 0.2V and that it is at 1 if its voltage is at 3.6V.
- Diodes D4, D5 and D6 have common anodes. So the diode that conducts is the one that will have the lowest cathode potential (<=> the one that will be the best forward biased because V (A) -V (K) will be the strongest).
- A = B = 0: D4 and D5 conduct => no current
Analysis:
A = B = 0:
- Suppose that D6 leads: this implies that T2 and T4 also lead => V (K) _D6 = Vbe_T2 + Vbe_T4 = 1.4 V.
Now as A = B = 0, we have V (K) _D4 = V (K) _D5 = 0.2V: So it is the diodes D4 and D5 which have the lowest cathode potential => they are the ones which conduct. So our guess was wrong: D4 and D5 are driving while D6 is stuck!
- Consequently Ib (T2) = 0 => T2 blocked => Ib (T4) = 0 => T4 blocked. On the other hand T3 leads:
- => V (Y) = Vcc – Ib (T3) * 1.6k – Vbe (T3) – V (D3) = 5 – 1600 * Ib (T3) – 0.6 – 0.7 = 3.7 – 1600 * Ib (T3) or Ib (T3) is so low in practice that we can say that 1600 * Ib (T3) is negligible => V (Y) = 3.7 V => Y = 1.
-In fact if at least one of the 2 inputs is at 0 then the diode corresponding to it will lead, and by exactly the same reasoning we will have Y = 1.
- A = B = 1:
- Suppose that D6 conduct => V (K) _D6 = 1.4 V (cf A = B = 0). as A = B = 1, we have V (K) _D4 = V (K) _D5 = 3.6V => D6 has the lowest cathode potential, so it conducts well. Our supposition is verified: D6 leads while D4 and D5 are blocked!
So T2 led => T4 led (we arrange for it to saturate in practice) => V (Y) = Vce_sat (T4) = 0.2V => Y = 0.
We find the operation of a NAND!
By door:
– consumption: 10 mW
– propagation time: 10 ns
